SCTL: Towards Combining Model Checking and Proof Checking

A Uniied Approach for Combining Diierent Formalisms for Hardware Veriication ?

Model Checking as the predominant technique for automatically verifying circuits suuers from the well-known state explosion problem. This hinders the veriication of circuits which contain non-trivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the control and data part prior to veriication. This paper is also based on this idea and presents an ap...

Towards a Formal Semantics of the TESL Specification Language

Most relevant industrial modeling problems depict heterogeneity issues when combining different paradigms. Designing such systems with discrete and continuous parts necessarily raises formal verification problems. We focus on a synchronous heterogeneous specification language, called TESL. In particular, it allows the expression of interrelations of clocks and — unlike other existing languages ...

Simulation Machines for Checking Action System Refinements

Action systems provide a formal approach to modelling parallel and reactive systems. They have a well established theory of refinement supported by simulation-based proof rules. This paper introduces an automatic approach for verifying action system refinements utilising standard CTL model checking. To do this, we encode each of the simulation conditions as a simulation machine, a Kripke struct...

Proof Checking and Approximation: towards Tight Results

Verifying Hardware Correctness by Combining Theorem Proving and Model Checking 1

In this paper, a veriication method is presented which combines the advantages of deduction style proof systems like HOL with those of traditional model checking approaches. For this reason, a new class of higher order formulas is presented, which allows a uniied description of hardware structure and behaviour at diierent levels of abstraction. Data path oriented veriication goals involving abs...